
select:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400668 <_init>:
  400668:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40066c:	910003fd 	mov	x29, sp
  400670:	9400004a 	bl	400798 <call_weak_fn>
  400674:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400678:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400680 <.plt>:
  400680:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400684:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x101a0>
  400688:	f947fe11 	ldr	x17, [x16, #4088]
  40068c:	913fe210 	add	x16, x16, #0xff8
  400690:	d61f0220 	br	x17
  400694:	d503201f 	nop
  400698:	d503201f 	nop
  40069c:	d503201f 	nop

00000000004006a0 <exit@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006a4:	f9400211 	ldr	x17, [x16]
  4006a8:	91000210 	add	x16, x16, #0x0
  4006ac:	d61f0220 	br	x17

00000000004006b0 <malloc@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006b4:	f9400611 	ldr	x17, [x16, #8]
  4006b8:	91002210 	add	x16, x16, #0x8
  4006bc:	d61f0220 	br	x17

00000000004006c0 <__libc_start_main@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006c4:	f9400a11 	ldr	x17, [x16, #16]
  4006c8:	91004210 	add	x16, x16, #0x10
  4006cc:	d61f0220 	br	x17

00000000004006d0 <rand@plt>:
  4006d0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006d4:	f9400e11 	ldr	x17, [x16, #24]
  4006d8:	91006210 	add	x16, x16, #0x18
  4006dc:	d61f0220 	br	x17

00000000004006e0 <__gmon_start__@plt>:
  4006e0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006e4:	f9401211 	ldr	x17, [x16, #32]
  4006e8:	91008210 	add	x16, x16, #0x20
  4006ec:	d61f0220 	br	x17

00000000004006f0 <abort@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006f4:	f9401611 	ldr	x17, [x16, #40]
  4006f8:	9100a210 	add	x16, x16, #0x28
  4006fc:	d61f0220 	br	x17

0000000000400700 <puts@plt>:
  400700:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400704:	f9401a11 	ldr	x17, [x16, #48]
  400708:	9100c210 	add	x16, x16, #0x30
  40070c:	d61f0220 	br	x17

0000000000400710 <fwrite@plt>:
  400710:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400714:	f9401e11 	ldr	x17, [x16, #56]
  400718:	9100e210 	add	x16, x16, #0x38
  40071c:	d61f0220 	br	x17

0000000000400720 <__isoc99_scanf@plt>:
  400720:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400724:	f9402211 	ldr	x17, [x16, #64]
  400728:	91010210 	add	x16, x16, #0x40
  40072c:	d61f0220 	br	x17

0000000000400730 <printf@plt>:
  400730:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400734:	f9402611 	ldr	x17, [x16, #72]
  400738:	91012210 	add	x16, x16, #0x48
  40073c:	d61f0220 	br	x17

0000000000400740 <putchar@plt>:
  400740:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400744:	f9402a11 	ldr	x17, [x16, #80]
  400748:	91014210 	add	x16, x16, #0x50
  40074c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400750 <_start>:
  400750:	d280001d 	mov	x29, #0x0                   	// #0
  400754:	d280001e 	mov	x30, #0x0                   	// #0
  400758:	aa0003e5 	mov	x5, x0
  40075c:	f94003e1 	ldr	x1, [sp]
  400760:	910023e2 	add	x2, sp, #0x8
  400764:	910003e6 	mov	x6, sp
  400768:	580000c0 	ldr	x0, 400780 <_start+0x30>
  40076c:	580000e3 	ldr	x3, 400788 <_start+0x38>
  400770:	58000104 	ldr	x4, 400790 <_start+0x40>
  400774:	97ffffd3 	bl	4006c0 <__libc_start_main@plt>
  400778:	97ffffde 	bl	4006f0 <abort@plt>
  40077c:	00000000 	.inst	0x00000000 ; undefined
  400780:	00400cf0 	.word	0x00400cf0
  400784:	00000000 	.word	0x00000000
  400788:	00400d08 	.word	0x00400d08
  40078c:	00000000 	.word	0x00000000
  400790:	00400d88 	.word	0x00400d88
  400794:	00000000 	.word	0x00000000

0000000000400798 <call_weak_fn>:
  400798:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x101a0>
  40079c:	f947f000 	ldr	x0, [x0, #4064]
  4007a0:	b4000040 	cbz	x0, 4007a8 <call_weak_fn+0x10>
  4007a4:	17ffffcf 	b	4006e0 <__gmon_start__@plt>
  4007a8:	d65f03c0 	ret
  4007ac:	00000000 	.inst	0x00000000 ; undefined

00000000004007b0 <deregister_tm_clones>:
  4007b0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007b4:	9101a000 	add	x0, x0, #0x68
  4007b8:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  4007bc:	9101a021 	add	x1, x1, #0x68
  4007c0:	eb00003f 	cmp	x1, x0
  4007c4:	540000a0 	b.eq	4007d8 <deregister_tm_clones+0x28>  // b.none
  4007c8:	90000001 	adrp	x1, 400000 <_init-0x668>
  4007cc:	f946d421 	ldr	x1, [x1, #3496]
  4007d0:	b4000041 	cbz	x1, 4007d8 <deregister_tm_clones+0x28>
  4007d4:	d61f0020 	br	x1
  4007d8:	d65f03c0 	ret
  4007dc:	d503201f 	nop

00000000004007e0 <register_tm_clones>:
  4007e0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007e4:	9101a000 	add	x0, x0, #0x68
  4007e8:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  4007ec:	9101a021 	add	x1, x1, #0x68
  4007f0:	cb000021 	sub	x1, x1, x0
  4007f4:	9343fc21 	asr	x1, x1, #3
  4007f8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4007fc:	9341fc21 	asr	x1, x1, #1
  400800:	b40000a1 	cbz	x1, 400814 <register_tm_clones+0x34>
  400804:	90000002 	adrp	x2, 400000 <_init-0x668>
  400808:	f946d842 	ldr	x2, [x2, #3504]
  40080c:	b4000042 	cbz	x2, 400814 <register_tm_clones+0x34>
  400810:	d61f0040 	br	x2
  400814:	d65f03c0 	ret

0000000000400818 <__do_global_dtors_aux>:
  400818:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40081c:	910003fd 	mov	x29, sp
  400820:	f9000bf3 	str	x19, [sp, #16]
  400824:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  400828:	3941c260 	ldrb	w0, [x19, #112]
  40082c:	35000080 	cbnz	w0, 40083c <__do_global_dtors_aux+0x24>
  400830:	97ffffe0 	bl	4007b0 <deregister_tm_clones>
  400834:	52800020 	mov	w0, #0x1                   	// #1
  400838:	3901c260 	strb	w0, [x19, #112]
  40083c:	f9400bf3 	ldr	x19, [sp, #16]
  400840:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400844:	d65f03c0 	ret

0000000000400848 <frame_dummy>:
  400848:	17ffffe6 	b	4007e0 <register_tm_clones>

000000000040084c <swap>:
  40084c:	d10083ff 	sub	sp, sp, #0x20
  400850:	f90007e0 	str	x0, [sp, #8]
  400854:	f90003e1 	str	x1, [sp]
  400858:	f94007e0 	ldr	x0, [sp, #8]
  40085c:	b9400000 	ldr	w0, [x0]
  400860:	b9001fe0 	str	w0, [sp, #28]
  400864:	f94003e0 	ldr	x0, [sp]
  400868:	b9400001 	ldr	w1, [x0]
  40086c:	f94007e0 	ldr	x0, [sp, #8]
  400870:	b9000001 	str	w1, [x0]
  400874:	f94003e0 	ldr	x0, [sp]
  400878:	b9401fe1 	ldr	w1, [sp, #28]
  40087c:	b9000001 	str	w1, [x0]
  400880:	d503201f 	nop
  400884:	910083ff 	add	sp, sp, #0x20
  400888:	d65f03c0 	ret

000000000040088c <select_sort>:
  40088c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400890:	910003fd 	mov	x29, sp
  400894:	a90153f3 	stp	x19, x20, [sp, #16]
  400898:	f90013f5 	str	x21, [sp, #32]
  40089c:	f9001fa0 	str	x0, [x29, #56]
  4008a0:	b90037a1 	str	w1, [x29, #52]
  4008a4:	52800013 	mov	w19, #0x0                   	// #0
  4008a8:	1400003b 	b	400994 <select_sort+0x108>
  4008ac:	2a1303f5 	mov	w21, w19
  4008b0:	11000674 	add	w20, w19, #0x1
  4008b4:	1400000f 	b	4008f0 <select_sort+0x64>
  4008b8:	93407ea0 	sxtw	x0, w21
  4008bc:	d37ef400 	lsl	x0, x0, #2
  4008c0:	f9401fa1 	ldr	x1, [x29, #56]
  4008c4:	8b000020 	add	x0, x1, x0
  4008c8:	b9400001 	ldr	w1, [x0]
  4008cc:	93407e80 	sxtw	x0, w20
  4008d0:	d37ef400 	lsl	x0, x0, #2
  4008d4:	f9401fa2 	ldr	x2, [x29, #56]
  4008d8:	8b000040 	add	x0, x2, x0
  4008dc:	b9400000 	ldr	w0, [x0]
  4008e0:	6b00003f 	cmp	w1, w0
  4008e4:	5400004d 	b.le	4008ec <select_sort+0x60>
  4008e8:	2a1403f5 	mov	w21, w20
  4008ec:	11000694 	add	w20, w20, #0x1
  4008f0:	b94037a0 	ldr	w0, [x29, #52]
  4008f4:	6b00029f 	cmp	w20, w0
  4008f8:	54fffe0b 	b.lt	4008b8 <select_sort+0x2c>  // b.tstop
  4008fc:	6b1302bf 	cmp	w21, w19
  400900:	54000480 	b.eq	400990 <select_sort+0x104>  // b.none
  400904:	93407ea0 	sxtw	x0, w21
  400908:	d37ef400 	lsl	x0, x0, #2
  40090c:	f9401fa1 	ldr	x1, [x29, #56]
  400910:	8b000022 	add	x2, x1, x0
  400914:	93407e60 	sxtw	x0, w19
  400918:	d37ef400 	lsl	x0, x0, #2
  40091c:	f9401fa1 	ldr	x1, [x29, #56]
  400920:	8b000020 	add	x0, x1, x0
  400924:	aa0003e1 	mov	x1, x0
  400928:	aa0203e0 	mov	x0, x2
  40092c:	97ffffc8 	bl	40084c <swap>
  400930:	11000661 	add	w1, w19, #0x1
  400934:	90000000 	adrp	x0, 400000 <_init-0x668>
  400938:	9136e000 	add	x0, x0, #0xdb8
  40093c:	97ffff7d 	bl	400730 <printf@plt>
  400940:	52800014 	mov	w20, #0x0                   	// #0
  400944:	1400000e 	b	40097c <select_sort+0xf0>
  400948:	7100029f 	cmp	w20, #0x0
  40094c:	5400006d 	b.le	400958 <select_sort+0xcc>
  400950:	52800400 	mov	w0, #0x20                  	// #32
  400954:	97ffff7b 	bl	400740 <putchar@plt>
  400958:	93407e80 	sxtw	x0, w20
  40095c:	d37ef400 	lsl	x0, x0, #2
  400960:	f9401fa1 	ldr	x1, [x29, #56]
  400964:	8b000020 	add	x0, x1, x0
  400968:	b9400001 	ldr	w1, [x0]
  40096c:	90000000 	adrp	x0, 400000 <_init-0x668>
  400970:	91376000 	add	x0, x0, #0xdd8
  400974:	97ffff6f 	bl	400730 <printf@plt>
  400978:	11000694 	add	w20, w20, #0x1
  40097c:	b94037a0 	ldr	w0, [x29, #52]
  400980:	6b00029f 	cmp	w20, w0
  400984:	54fffe2b 	b.lt	400948 <select_sort+0xbc>  // b.tstop
  400988:	52800140 	mov	w0, #0xa                   	// #10
  40098c:	97ffff6d 	bl	400740 <putchar@plt>
  400990:	11000673 	add	w19, w19, #0x1
  400994:	b94037a0 	ldr	w0, [x29, #52]
  400998:	51000400 	sub	w0, w0, #0x1
  40099c:	6b00027f 	cmp	w19, w0
  4009a0:	54fff86b 	b.lt	4008ac <select_sort+0x20>  // b.tstop
  4009a4:	d503201f 	nop
  4009a8:	a94153f3 	ldp	x19, x20, [sp, #16]
  4009ac:	f94013f5 	ldr	x21, [sp, #32]
  4009b0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4009b4:	d65f03c0 	ret

00000000004009b8 <select_sort_test>:
  4009b8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4009bc:	910003fd 	mov	x29, sp
  4009c0:	14000035 	b	400a94 <select_sort_test+0xdc>
  4009c4:	b9401fa0 	ldr	w0, [x29, #28]
  4009c8:	93407c00 	sxtw	x0, w0
  4009cc:	d37ef400 	lsl	x0, x0, #2
  4009d0:	97ffff38 	bl	4006b0 <malloc@plt>
  4009d4:	f90013a0 	str	x0, [x29, #32]
  4009d8:	b9002fbf 	str	wzr, [x29, #44]
  4009dc:	1400000b 	b	400a08 <select_sort_test+0x50>
  4009e0:	b9802fa0 	ldrsw	x0, [x29, #44]
  4009e4:	d37ef400 	lsl	x0, x0, #2
  4009e8:	f94013a1 	ldr	x1, [x29, #32]
  4009ec:	8b000021 	add	x1, x1, x0
  4009f0:	90000000 	adrp	x0, 400000 <_init-0x668>
  4009f4:	91378000 	add	x0, x0, #0xde0
  4009f8:	97ffff4a 	bl	400720 <__isoc99_scanf@plt>
  4009fc:	b9402fa0 	ldr	w0, [x29, #44]
  400a00:	11000400 	add	w0, w0, #0x1
  400a04:	b9002fa0 	str	w0, [x29, #44]
  400a08:	b9401fa0 	ldr	w0, [x29, #28]
  400a0c:	b9402fa1 	ldr	w1, [x29, #44]
  400a10:	6b00003f 	cmp	w1, w0
  400a14:	54fffe6b 	b.lt	4009e0 <select_sort_test+0x28>  // b.tstop
  400a18:	b9401fa0 	ldr	w0, [x29, #28]
  400a1c:	2a0003e1 	mov	w1, w0
  400a20:	f94013a0 	ldr	x0, [x29, #32]
  400a24:	97ffff9a 	bl	40088c <select_sort>
  400a28:	90000000 	adrp	x0, 400000 <_init-0x668>
  400a2c:	9137a000 	add	x0, x0, #0xde8
  400a30:	97ffff34 	bl	400700 <puts@plt>
  400a34:	b9002fbf 	str	wzr, [x29, #44]
  400a38:	14000011 	b	400a7c <select_sort_test+0xc4>
  400a3c:	b9402fa0 	ldr	w0, [x29, #44]
  400a40:	7100001f 	cmp	w0, #0x0
  400a44:	5400006d 	b.le	400a50 <select_sort_test+0x98>
  400a48:	52800400 	mov	w0, #0x20                  	// #32
  400a4c:	97ffff3d 	bl	400740 <putchar@plt>
  400a50:	b9802fa0 	ldrsw	x0, [x29, #44]
  400a54:	d37ef400 	lsl	x0, x0, #2
  400a58:	f94013a1 	ldr	x1, [x29, #32]
  400a5c:	8b000020 	add	x0, x1, x0
  400a60:	b9400001 	ldr	w1, [x0]
  400a64:	90000000 	adrp	x0, 400000 <_init-0x668>
  400a68:	91376000 	add	x0, x0, #0xdd8
  400a6c:	97ffff31 	bl	400730 <printf@plt>
  400a70:	b9402fa0 	ldr	w0, [x29, #44]
  400a74:	11000400 	add	w0, w0, #0x1
  400a78:	b9002fa0 	str	w0, [x29, #44]
  400a7c:	b9401fa0 	ldr	w0, [x29, #28]
  400a80:	b9402fa1 	ldr	w1, [x29, #44]
  400a84:	6b00003f 	cmp	w1, w0
  400a88:	54fffdab 	b.lt	400a3c <select_sort_test+0x84>  // b.tstop
  400a8c:	52800140 	mov	w0, #0xa                   	// #10
  400a90:	97ffff2c 	bl	400740 <putchar@plt>
  400a94:	910073a1 	add	x1, x29, #0x1c
  400a98:	90000000 	adrp	x0, 400000 <_init-0x668>
  400a9c:	91378000 	add	x0, x0, #0xde0
  400aa0:	97ffff20 	bl	400720 <__isoc99_scanf@plt>
  400aa4:	3100041f 	cmn	w0, #0x1
  400aa8:	54fff8e1 	b.ne	4009c4 <select_sort_test+0xc>  // b.any
  400aac:	52800000 	mov	w0, #0x0                   	// #0
  400ab0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ab4:	d65f03c0 	ret

0000000000400ab8 <select_sort_other>:
  400ab8:	d10083ff 	sub	sp, sp, #0x20
  400abc:	f90007e0 	str	x0, [sp, #8]
  400ac0:	b90007e1 	str	w1, [sp, #4]
  400ac4:	b9001fff 	str	wzr, [sp, #28]
  400ac8:	14000035 	b	400b9c <select_sort_other+0xe4>
  400acc:	b9401fe0 	ldr	w0, [sp, #28]
  400ad0:	b90017e0 	str	w0, [sp, #20]
  400ad4:	b9401fe0 	ldr	w0, [sp, #28]
  400ad8:	11000400 	add	w0, w0, #0x1
  400adc:	b9001be0 	str	w0, [sp, #24]
  400ae0:	14000012 	b	400b28 <select_sort_other+0x70>
  400ae4:	b9801be0 	ldrsw	x0, [sp, #24]
  400ae8:	d37ef400 	lsl	x0, x0, #2
  400aec:	f94007e1 	ldr	x1, [sp, #8]
  400af0:	8b000020 	add	x0, x1, x0
  400af4:	b9400001 	ldr	w1, [x0]
  400af8:	b98017e0 	ldrsw	x0, [sp, #20]
  400afc:	d37ef400 	lsl	x0, x0, #2
  400b00:	f94007e2 	ldr	x2, [sp, #8]
  400b04:	8b000040 	add	x0, x2, x0
  400b08:	b9400000 	ldr	w0, [x0]
  400b0c:	6b00003f 	cmp	w1, w0
  400b10:	5400006a 	b.ge	400b1c <select_sort_other+0x64>  // b.tcont
  400b14:	b9401be0 	ldr	w0, [sp, #24]
  400b18:	b90017e0 	str	w0, [sp, #20]
  400b1c:	b9401be0 	ldr	w0, [sp, #24]
  400b20:	11000400 	add	w0, w0, #0x1
  400b24:	b9001be0 	str	w0, [sp, #24]
  400b28:	b9401be1 	ldr	w1, [sp, #24]
  400b2c:	b94007e0 	ldr	w0, [sp, #4]
  400b30:	6b00003f 	cmp	w1, w0
  400b34:	54fffd8b 	b.lt	400ae4 <select_sort_other+0x2c>  // b.tstop
  400b38:	b9801fe0 	ldrsw	x0, [sp, #28]
  400b3c:	d37ef400 	lsl	x0, x0, #2
  400b40:	f94007e1 	ldr	x1, [sp, #8]
  400b44:	8b000020 	add	x0, x1, x0
  400b48:	b9400000 	ldr	w0, [x0]
  400b4c:	b90013e0 	str	w0, [sp, #16]
  400b50:	b98017e0 	ldrsw	x0, [sp, #20]
  400b54:	d37ef400 	lsl	x0, x0, #2
  400b58:	f94007e1 	ldr	x1, [sp, #8]
  400b5c:	8b000021 	add	x1, x1, x0
  400b60:	b9801fe0 	ldrsw	x0, [sp, #28]
  400b64:	d37ef400 	lsl	x0, x0, #2
  400b68:	f94007e2 	ldr	x2, [sp, #8]
  400b6c:	8b000040 	add	x0, x2, x0
  400b70:	b9400021 	ldr	w1, [x1]
  400b74:	b9000001 	str	w1, [x0]
  400b78:	b98017e0 	ldrsw	x0, [sp, #20]
  400b7c:	d37ef400 	lsl	x0, x0, #2
  400b80:	f94007e1 	ldr	x1, [sp, #8]
  400b84:	8b000020 	add	x0, x1, x0
  400b88:	b94013e1 	ldr	w1, [sp, #16]
  400b8c:	b9000001 	str	w1, [x0]
  400b90:	b9401fe0 	ldr	w0, [sp, #28]
  400b94:	11000400 	add	w0, w0, #0x1
  400b98:	b9001fe0 	str	w0, [sp, #28]
  400b9c:	b94007e0 	ldr	w0, [sp, #4]
  400ba0:	51000400 	sub	w0, w0, #0x1
  400ba4:	b9401fe1 	ldr	w1, [sp, #28]
  400ba8:	6b00003f 	cmp	w1, w0
  400bac:	54fff90b 	b.lt	400acc <select_sort_other+0x14>  // b.tstop
  400bb0:	d503201f 	nop
  400bb4:	910083ff 	add	sp, sp, #0x20
  400bb8:	d65f03c0 	ret

0000000000400bbc <select_sort_other_test>:
  400bbc:	a9a57bfd 	stp	x29, x30, [sp, #-432]!
  400bc0:	910003fd 	mov	x29, sp
  400bc4:	90000000 	adrp	x0, 400000 <_init-0x668>
  400bc8:	91380000 	add	x0, x0, #0xe00
  400bcc:	97fffed9 	bl	400730 <printf@plt>
  400bd0:	9106a3a1 	add	x1, x29, #0x1a8
  400bd4:	90000000 	adrp	x0, 400000 <_init-0x668>
  400bd8:	91378000 	add	x0, x0, #0xde0
  400bdc:	97fffed1 	bl	400720 <__isoc99_scanf@plt>
  400be0:	b941aba0 	ldr	w0, [x29, #424]
  400be4:	7100001f 	cmp	w0, #0x0
  400be8:	5400008d 	b.le	400bf8 <select_sort_other_test+0x3c>
  400bec:	b941aba0 	ldr	w0, [x29, #424]
  400bf0:	7101941f 	cmp	w0, #0x65
  400bf4:	5400018d 	b.le	400c24 <select_sort_other_test+0x68>
  400bf8:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400bfc:	9101a000 	add	x0, x0, #0x68
  400c00:	f9400001 	ldr	x1, [x0]
  400c04:	90000000 	adrp	x0, 400000 <_init-0x668>
  400c08:	9138c000 	add	x0, x0, #0xe30
  400c0c:	aa0103e3 	mov	x3, x1
  400c10:	d2800282 	mov	x2, #0x14                  	// #20
  400c14:	d2800021 	mov	x1, #0x1                   	// #1
  400c18:	97fffebe 	bl	400710 <fwrite@plt>
  400c1c:	52800020 	mov	w0, #0x1                   	// #1
  400c20:	97fffea0 	bl	4006a0 <exit@plt>
  400c24:	b901afbf 	str	wzr, [x29, #428]
  400c28:	14000013 	b	400c74 <select_sort_other_test+0xb8>
  400c2c:	97fffea9 	bl	4006d0 <rand@plt>
  400c30:	2a0003e1 	mov	w1, w0
  400c34:	52807d00 	mov	w0, #0x3e8                 	// #1000
  400c38:	1b007c22 	mul	w2, w1, w0
  400c3c:	b981afa0 	ldrsw	x0, [x29, #428]
  400c40:	d37ef400 	lsl	x0, x0, #2
  400c44:	910043a1 	add	x1, x29, #0x10
  400c48:	b8206822 	str	w2, [x1, x0]
  400c4c:	b981afa0 	ldrsw	x0, [x29, #428]
  400c50:	d37ef400 	lsl	x0, x0, #2
  400c54:	910043a1 	add	x1, x29, #0x10
  400c58:	b8606821 	ldr	w1, [x1, x0]
  400c5c:	90000000 	adrp	x0, 400000 <_init-0x668>
  400c60:	91392000 	add	x0, x0, #0xe48
  400c64:	97fffeb3 	bl	400730 <printf@plt>
  400c68:	b941afa0 	ldr	w0, [x29, #428]
  400c6c:	11000400 	add	w0, w0, #0x1
  400c70:	b901afa0 	str	w0, [x29, #428]
  400c74:	b941aba0 	ldr	w0, [x29, #424]
  400c78:	b941afa1 	ldr	w1, [x29, #428]
  400c7c:	6b00003f 	cmp	w1, w0
  400c80:	54fffd6b 	b.lt	400c2c <select_sort_other_test+0x70>  // b.tstop
  400c84:	b941aba1 	ldr	w1, [x29, #424]
  400c88:	910043a0 	add	x0, x29, #0x10
  400c8c:	97ffff8b 	bl	400ab8 <select_sort_other>
  400c90:	90000000 	adrp	x0, 400000 <_init-0x668>
  400c94:	91394000 	add	x0, x0, #0xe50
  400c98:	97fffe9a 	bl	400700 <puts@plt>
  400c9c:	b901afbf 	str	wzr, [x29, #428]
  400ca0:	1400000b 	b	400ccc <select_sort_other_test+0x110>
  400ca4:	b981afa0 	ldrsw	x0, [x29, #428]
  400ca8:	d37ef400 	lsl	x0, x0, #2
  400cac:	910043a1 	add	x1, x29, #0x10
  400cb0:	b8606821 	ldr	w1, [x1, x0]
  400cb4:	90000000 	adrp	x0, 400000 <_init-0x668>
  400cb8:	91392000 	add	x0, x0, #0xe48
  400cbc:	97fffe9d 	bl	400730 <printf@plt>
  400cc0:	b941afa0 	ldr	w0, [x29, #428]
  400cc4:	11000400 	add	w0, w0, #0x1
  400cc8:	b901afa0 	str	w0, [x29, #428]
  400ccc:	b941aba0 	ldr	w0, [x29, #424]
  400cd0:	b941afa1 	ldr	w1, [x29, #428]
  400cd4:	6b00003f 	cmp	w1, w0
  400cd8:	54fffe6b 	b.lt	400ca4 <select_sort_other_test+0xe8>  // b.tstop
  400cdc:	52800140 	mov	w0, #0xa                   	// #10
  400ce0:	97fffe98 	bl	400740 <putchar@plt>
  400ce4:	d503201f 	nop
  400ce8:	a8db7bfd 	ldp	x29, x30, [sp], #432
  400cec:	d65f03c0 	ret

0000000000400cf0 <main>:
  400cf0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400cf4:	910003fd 	mov	x29, sp
  400cf8:	97ffffb1 	bl	400bbc <select_sort_other_test>
  400cfc:	52800000 	mov	w0, #0x0                   	// #0
  400d00:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400d04:	d65f03c0 	ret

0000000000400d08 <__libc_csu_init>:
  400d08:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d0c:	910003fd 	mov	x29, sp
  400d10:	a901d7f4 	stp	x20, x21, [sp, #24]
  400d14:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x101a0>
  400d18:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x101a0>
  400d1c:	91374294 	add	x20, x20, #0xdd0
  400d20:	913722b5 	add	x21, x21, #0xdc8
  400d24:	a902dff6 	stp	x22, x23, [sp, #40]
  400d28:	cb150294 	sub	x20, x20, x21
  400d2c:	f9001ff8 	str	x24, [sp, #56]
  400d30:	2a0003f6 	mov	w22, w0
  400d34:	aa0103f7 	mov	x23, x1
  400d38:	9343fe94 	asr	x20, x20, #3
  400d3c:	aa0203f8 	mov	x24, x2
  400d40:	97fffe4a 	bl	400668 <_init>
  400d44:	b4000194 	cbz	x20, 400d74 <__libc_csu_init+0x6c>
  400d48:	f9000bb3 	str	x19, [x29, #16]
  400d4c:	d2800013 	mov	x19, #0x0                   	// #0
  400d50:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400d54:	aa1803e2 	mov	x2, x24
  400d58:	aa1703e1 	mov	x1, x23
  400d5c:	2a1603e0 	mov	w0, w22
  400d60:	91000673 	add	x19, x19, #0x1
  400d64:	d63f0060 	blr	x3
  400d68:	eb13029f 	cmp	x20, x19
  400d6c:	54ffff21 	b.ne	400d50 <__libc_csu_init+0x48>  // b.any
  400d70:	f9400bb3 	ldr	x19, [x29, #16]
  400d74:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400d78:	a942dff6 	ldp	x22, x23, [sp, #40]
  400d7c:	f9401ff8 	ldr	x24, [sp, #56]
  400d80:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400d84:	d65f03c0 	ret

0000000000400d88 <__libc_csu_fini>:
  400d88:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400d8c <_fini>:
  400d8c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400d90:	910003fd 	mov	x29, sp
  400d94:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400d98:	d65f03c0 	ret
